This invention relates to a method and an apparatus for testing the function of an integrated circuit (hereinafter called a "IC").
FIG. 8 is a circuit diagram illustrating an internal discriminating circuit of a known function testing apparatus for testing the function of an IC. As illustrated in FIG. 8, reference numeral 9 designates an IC to be tested concerning its functions in the function test. When the function test is performed, the IC 9 is electrically connected to an internal discriminating circuit of the known function testing apparatus by a testing pin 14 so that the IC 9 is tested. FIG. 6 is a block diagram of the IC 9. The structure of the discriminating circuit of the known function testing apparatus will now be described, which comprises a reference signal generating unit 1 for generating a reference signal (hereinafter called a "DO") for the function testing apparatus, a start-timing signal generating circuit 2 (hereinafter called a "SET generating circuit") for generating a discrimination start-timing signal (hereinafter called a "SET"), a completion timing signal generating circuit 3 (hereinafter called a "RESET generating circuit") for generating a discrimination completion-timing signal (hereinafter called "RESET"), and a RS-flip-flop 4 for generating a discrimination range signal (hereinafter called "WIND") indicating a discrimination time range by using the timing signal SET generated by the SET generating circuit 2 and the completion-timing signal RESET generated by the RESET generating circuit 3. The discriminating circuit of the testing apparatus further comprises a test pattern memory 5 for storing test pattern data (hereinafter called "DATA") for switching between high level discrimination and low level discrimination, and a D-flip-flop 6 for generating a signal (hereinafter called "SDATA") by latching the test pattern data DATA transmitted from the test pattern memory 5 by the timing signal SET from the SET generating circuit 2. The discriminating circuit of the testing apparatus still further comprises an AND gate 7 for generating the logical product signal (hereinafter called "HWIND") indicating the logical product of the discrimination range signal WIND supplied from the RS-flip-flop 4 and the signal SDATA supplied from the D-flip-flop 6, and another AND gate 8 for generating a logical product signal (hereinafter called "LWIND") indicating the logical product of the discrimination range signal WIND and inverse signal SDATA of SDATA.
Reference numeral 10 designates a high-level comparative voltage generating circuit for receiving a predicted high-level comparative voltage data transmitted from a control circuit 19 which controls the function testing apparatus and supplying a high-level comparative voltage corresponding to the data from the control circuit 9, 11 is a potential comparison circuit for generating a high-level comparative signal (hereinafter called "HCOM") by comparing a potential of a output voltage (hereinafter called "DOUT") supplied from the IC 9 to be tested with the potential of the high level comparative voltage, 12 is a low-level comparative voltage generating circuit for receiving predicted low-level comparative voltage data transmitted from the control circuit 19 and supplying a low level comparative voltage corresponding to the transmitted data from the control circuit 19, 13 is a potential comparison circuit for generating a low-level comparative signal (hereinafter called "LCOM") by comparing the potential of the output voltage DOUT from the IC 9 to be tested with the potential of the low-level comparative voltage, 15 is an AND gate for generating a high-level defective signal (hereinafter called "HERR 1") which is the logical product of the comparative signal HCOM supplied from the potential comparison circuit 11 and the logical product signal HWIND supplied from the AND gate 7, 16 is an AND gate for generating a low-level defective signal (hereinafter called "LERR 1") which is the logical product of the comparative signal LCOM supplied from the potential comparison circuit 13 and the logical product signal LWIND supplied from the AND gate 8, 17 is a latch circuit for latching the signal HERR 1, 18 is a latch circuit for latching the signal LERR 1, 20 is a signal line for transmitting the latched signal HERR 1 latched by the latch circuit 17 to the control circuit 19, 21 is also a signal line for transmitting the latched signal LERR 1 latched by the latch circuit 18 to the control unit 19, and 22 is a signal line for transmitting set data supplied from the control circuit 19 to the SET generating circuit 2, the RESET generating circuit 3, the test pattern memory 5 and the voltage generating circuits 10 and 12.
The operation of the discriminating circuit of the known IC function testing apparatus shown in FIG. 8 will now be described. A process to be performed before the function test is carried out will now be described. The control circuit 19, through the signal line 22, transmits to the SET generating circuit 2 the start-timing data with which the RS-flip-flop 4 supplies the discrimination range signal WIND, transmits to the RESET generating circuit 3 the completion timing data with which the RS-flip-flop 4 stops supplying the discrimination range signal WIND, transmits to the test pattern memory 5 all test pattern data DATA required to test the functions, transmits to the voltage generating circuit 10 the predicted high-level comparative voltage data, and transmits to the voltage generating circuit 12 the predicted low-level comparative voltage data.
A process to be performed during the function test will now be described. FIG. 9 is a timing chart of the operation timing of the discrimination circuit of the IC function testing apparatus. The SET generating circuit 2 receives the reference signal DO from the reference signal generating unit 1, delays the reference signal DO in a time interval corresponding to quantity of the start-timing data transmitted from the control circuit 19 and generates the discrimination start-timing signal SET. The RESET generating circuit 3 receives the reference signal DO supplied from the reference signal generating unit 1, delays the reference signal DO in a time interval corresponding to the quantity of the completion timing data transmitted from the control circuit 19 and supplies the discrimination completion timing signal RESET. The RS-flip-flop 4 receives the timing signals SET and RESET and generates the discrimination range signal WIND. The discrimination start timing signal SET serves as the set input for the RS-flip-flop 4, and the discrimination completion timing signal RESET serves as the reset input for the RS-flip-flop 4. That is, the discrimination range signal WIND becomes a high level signal during a period from the rise time of the SET to the rise time of the RESET as shown in FIG. 9. The test pattern memory 5 triggers the reference signal DO as to sequentially supply the test pattern data DATA. The D-flip-flop 6 receives the test pattern data DATA transmitted from the test pattern memory 5 and the discrimination start timing signal SET as to supply the signal SDATA. The test pattern data DATA is a data input, and the timing signal SET is a clock input. Therefore, the signal SDATA is generated by latching the test pattern data DATA at the rise time of the timing signal SET. As a result, information of the signal SDATA is held to the rise time of the next SET, exceeding the period. When the level of the discrimination range signal WIND is high while the level of SDATA is high as shown in the N th period in FIG. 9, the AND gate 7 receives the discrimination range signal WIND and outputs the logical product signal HWIND at a high level. Therefore, a high-level discrimination is performed in the period in which the level of the logical product signal HWIND is high. When the level of the discrimination range signal WIND is high during the period in which the level of SDATA is low as shown in the N+1th period in FIG. 9, the AND gate 8 receives the discrimination range signal WIND and outputs the logical product signal LWIND at the high level. Therefore, a low-level discrimination is performed in the period in which the level of the logical product signal LWIND is high.
The function test evaluation is defined such that a defective high level discrimination is made when the potential of the output voltage DOUT from the IC 9 becomes higher than the high-level comparative voltage in the high level discrimination period, and a defective low level discrimination is made when the potential of the output voltage DOUT from the IC 9 becomes lower than the low-level comparative voltage in the low level discrimination period. The voltage generating circuit 10 generates a high-level comparative voltage corresponding to the predicted comparative high-level voltage data supplied from the control circuit 19. The voltage comparison circuit 11 supplies the comparative signal HCOM by receiving the high-level comparative voltage at a positive comparison terminal thereof and the output voltage DOUT from the IC 9 at a negative comparison terminal thereof and compares the high-level comparative voltage and the output voltage DOUT from the IC 9. The level of the comparative signal HCOM becomes high when the potential of the output voltage DOUT from the IC 9 is higher than that of the high-level comparative voltage, on the other hand, the same becomes low in a case contrary to this. The AND gate 15 receives the logical product signal HWIND transmitted from the AND gate 7 and the comparative signal HCOM as to generate the signal HERR 1. As shown in the Nth period in FIG. 9, the AND gate 15 transmits high level HERR 1 when the level of the comparative signal HCOM is high during the period in which the logical product signal HWIND is high. Therefore, the AND gate 15 notifies that there was a time period, in which the defective high level discrimination was made, during the high level discrimination period, and the discrimination was made in accordance with the result of the comparison with the high level voltage made by the voltage comparison circuit 11. The latch circuit 17 latches HERR 1 as to transmit, to the control circuit 19 through the signal line 50, information denoting that the high-level defective discrimination has been made.
The voltage generating circuit 12 generates the low-level comparative voltage that corresponds to the predicted comparative low-level voltage data transmitted from the control circuit 19. The voltage comparison circuit 13 receives the output voltage DOUT of the IC 9 at the positive comparison terminal thereof and the low-level comparative voltage at the negative comparison terminal thereof so as to compare the low-level comparative voltage and the output voltage DOUT of the IC 9 to supply the comparative signal LCOM. The level of the comparative signal LCOM becomes high when the output voltage DOUT from the IC 9 is lower than the low-level comparative voltage. The same becomes low in the contrary case. According to the illustrated example of the output, the AND gate 16 transmits high level LERR 1 when the level of the comparative signal LCOM is high during the period in which the logical product signal LWIND is high as shown in the N+1th period in FIG. 9. That is, the AND gate 16 notifies that a time period, in which the defective low level discrimination was made, was present during the low level discrimination period, the discrimination being made in accordance with the result of the comparison of the low level voltage made by the voltage comparison circuit 13. The latch circuit 18 latches LERR 1 as to transmit, to the control circuit 19 through the signal line 21, information denoting that the low-level defective discrimination has been made. As a result, the information denoting that the high-level defective discrimination has been made and the information denoting that the low-level defective discrimination has been made are used by the control circuit 19 to recognize the result of the function test to which the IC 9 has been subjected whether the result was satisfactory or defective.
When the RESET is set up to exceed the period as shown in FIG. 10, SDATA latched at the rise time of the discrimination start timing signal SET in the N th period is held to the rise time of the discrimination start timing signal SET at the N+1th period. The high level period of the discrimination range signal WIND is from the rise timing of the discrimination start timing signal SET in the N th period to the rise timing of the discrimination completion timing signal RESET in the N+1th period. The AND gate 7 transmits the logical product signal HWIND exceeding two periods in accordance with SDATA and the discrimination range signal WIND. As a result, the discrimination circuit of the IC function testing apparatus can carry out the high level discrimination exceeding the two periods. Also, the AND gate 8 transmits the logical product signal LWIND exceeding the two periods as a result of a similar arrangement as shown from the N+1th period to the N+2th period. Therefore, the discrimination circuit of the IC function testing apparatus is able to discriminate the low level exceeding the two periods.
In the trend of lowering the potential of the integrated circuits, tests have been performed to realize the electrical characteristics of the integrated circuits at low voltage levels. Therefore, function tests are sometimes performed in such a manner that low potential voltage is applied to a power supply voltage Vcc of the IC. However, the change of the Vcc results in the electrical characteristics of the IC 9 changing the output timing of the output data DOUT from the IC 9 as shown in FIG. 7. That is, the output timing for the output voltage DOUT is delayed for .DELTA.T when the Vcc is a low voltage as compared with a case where it is a high voltage. Since the known IC discriminating circuit for performing the function test has been constituted as described above, a problem arises in that data for setting the timing for the SET generating circuit 2 and that for the RESET generating circuit 3 must be changed to change the discrimination region according to the change in the output timing of the output data DOUT from the IC 9 between the two cases where the function test is performed by applying a high voltage Vcc and applying a low voltage Vcc.
Output data is defined as DOUT 1 when the function test is performed while applying a high a voltage Vcc of the IC 9 to be tested as shown in the N th period in FIG. 11. In this case, the region, in which the level of HWIND is high, that is, the high level discrimination region, includes no time region in which the high level comparative signal HCOM is high. Therefore, the high level voltage comparison performed by the voltage comparison circuit 11 is results in an output voltage DOUT 1 from the IC 9 to be tested that does not exceed the high level comparative voltage. As a result, no high level HERR 1 is transmitted, and therefore no time region is present in which the defective high region is discriminated. However, when low voltage is applied as the power supply voltage Vcc to perform the function test, the output voltage DOUT II from the IC 9 to be tested is delayed for .DELTA.T.sub.11 as shown in FIG. 11. It leads to a fact that the time region in which the level of HCOM is high is delayed. As a result, the high level discrimination region inevitably includes the time region in which the level of the high level comparative signal HCOM is high. As a result, HERR 1 having a high level is transmitted in the above time region as shown by a dashed line, and therefore a defective high level is undesirably indicated.
When the function test is performed while applying high voltage, no time region, in which the high level LCOM is transmitted, is present in the low level discrimination region as shown in the N+1th period shown in FIG. 11. Therefore, no high level LERR 1 is transmitted, and therefore no time region is present in which the defective low level discrimination is made. However, when the test is performed by applying low voltage, the output voltage DOUT II from the IC 9 is undesirably delayed for .DELTA.T.sub.11. In this case a time region is present, in which high level LCOM is transmitted in the low level discrimination region. As a result, the high level LERR 1 is transmitted in the above time region as designated by a dashed line, and therefore the defective low level is undesirably discriminated.